Enhanced read and write methods for negative differential resistance (NDR) based memory device

ABSTRACT

An enhanced method of writing and reading a memory device, such as an SRAM using negative differential resistance (NDR) elements), is disclosed. This is done through selective control of biasing of the active elements in a memory cell. For example in a write operation, a memory cell is placed in an intermediate state to increase write speed. In an NDR based embodiments, this is done by reducing a bias voltage to NDR FETs so as to weaken the NDR element (and thus disable an NDR effect) during the write operation. Conversely, during a read operation, the bias voltages are increased to enhance peak current (as well as an NDR effect), and thus provide additional current drive to a BIT line. Embodiments using such procedures achieve superior peak to valley current ratios (PVR), read/write speed, etc.

FIELD OF THE INVENTION

This invention generally relates to methods of operating semiconductormemory devices and technology, and in particular to read/writeoperations for static random access memory (SRAM) devices that utilizenegative differential resistance (NDR) elements.

BACKGROUND OF THE INVENTION

A new type of SRAM device using Negative Differential Resistance FieldEffect Transistors (NDR FETs) is described in detail in a patentapplication Ser. No. 10/029,077 filed Dec. 21, 2001 by T J King andassigned to the present assignee, and published on May 9, 2002 asPublication No. 2002/0054502. The NDR FET structure, operation andmethod of making the same are discussed in detail in patent applicationSer. No. 09/603,101 filed Jun. 22, 2000 by King et al., which is alsoassigned to the present assignee. Such details are also disclosed in acorresponding PCT application PCT/US01/19825 which was published aspublication no. WO 01/99153 on Dec. 27, 2001. The above materials arehereby incorporated by reference.

As is well-known in the art, some of the important benchmarks for memorydevices that determine the suitability for a particular applicationinclude the quiescent power rating, read speed and write speed.Futhermore, the peak-to-valley ratio (PVR) of the operating andquiescent current for a cell is also a significant factor that limitsthe feasibility of certain embodiments. For many applications it isbelieved that a PVR must exceed 10,000 to be practical at commerciallydesirable densities (i.e., in the MB range and above). Thus, it isapparent that the aforementioned NDR based SRAMs (and other NDR basedmemories) would also benefit from an increase in operating performanceof the NDR elements to meet the aforementioned benchmarks.

SUMMARY OF THE INVENTION

An object of the present invention is to provide operating methods thatimprove characteristics of a memory device, including particularly thosethat incorporate static random access memory (SRAM) cells which utilizeNDR FET elements.

A first aspect of the invention therefore concerns a method of operatinga memory cell that includes a negative differential resistance (NDR)capable element. This generally includes the following steps: applying abias signal to the NDR-capable element, during a first operation periodin which the memory cell is storing a data value, to enable theNDR-capable element to operate with an NDR characteristic. This NDRcharacteristic is adjusted to facilitate storing of the data value inthe memory cell during a first storage operation. During a secondoperation (i.e., such as a write operation) the bias signal is adjustedso as to lower the peak current (and thus also disable the NDRcharacteristic) immediately prior to and/or during the second operation.

In a preferred approach, the NDR-capable element is an NDR field effecttransistor (FET) and the NDR characteristic is exhibited in a channelregion of the NDR FET. In this manner, the bias signal is applied to agate of the NDR FET and is adjusted so that the peak current issubstantially lowered. Further in a preferred approach, the bias signalis adjusted immediately during the second operation period to re-enablethe NDR characteristic and facilitate storing of a new data valuewritten to the memory cell.

Another aspect of the invention concerns a method of operating a memorycell that exhibits variable NDR behavior during a write operation. Thisis achieved by applying a bias signal to the NDR element during a firstperiod in which the memory cell is storing a data value. In thisoperational state, the bias signal has a first signal characteristicduring the first period (for example, a high voltage level) so as tocontrol the NDR element to have a first operating characteristic (forexample, to enable an NDR behavior). During a second period, the biassignal is adjusted to have a second signal characteristic so as tocontrol the NDR element to have a second operating characteristic (forexample, to lower the peak current and disable the NDR behavior)immediately prior to and/or during a write operation associated with thememory cell.

Accordingly, in a preferred approach, the first signal characteristic isa first signal voltage amplitude level associated with the bias signal,and the second signal characteristic is a second signal voltageamplitude level associated with the bias signal. The first signalvoltage amplitude level is greater than the second signal voltageamplitude level so that the first operating characteristic includes anNDR operating region and the second NDR characteristic exhibits lowerpeak current and may or may not include an NDR operating region.

Further in a preferred embodiment, the data value is erased before thewrite operation effectuates writing of a subsequent data value to thememory cell.

Finally, a preferred memory cell of this invention uses both a first NDRelement (as a pull-up element) and a second NDR element (a pull-downelement) connected in series to a storage node and the first NDRelement. In such instances, the bias signal is applied to the second NDRelement as well as the first NDR element at substantially the same timeduring the first period and the second period.

Yet another aspect of the invention pertains to operating a memory cell(including NDR variations) to use an indeterminate state during a writeoperation. This is accomplished by applying a bias signal to an NDR FET(in the memory cell) to cause it to operate with an NDR characteristicwhile the cell is storing a particular first data value. Later, andimmediately proceeding a write operation, the first data value stored inthe memory cell is effectively “erased” by adjusting the bias signal todisable the NDR characteristic. In other words, the first data value ispreferably represented by a first voltage potential or a second voltagepotential present in a storage node of the memory cell, and during theerasing step the storage node is set to a third voltage potential.Notably, this third voltage potential is set without regard to a voltagepotential associated with a second data value to be written to thememory cell, and is caused by disabling the NDR characteristic of theFET. This then results in an indeterminate state for the storage nodethat lies somewhere between the first voltage potential and the secondpotential. The final value is not critical to this aspect of theinvention. During the actual write operation, the second data value iswritten to the memory cell so that the storage node is adjusted from thethird voltage potential (either up or down) to one of at least the firstvoltage potential or the second voltage potential.

In a preferred embodiment, the cell is designed and operated so that thethird voltage potential corresponds to a voltage potential that isapproximately half-way between the first voltage potential and thesecond voltage potential. This ensures that (for random data at least),the overall current consumed is reduced.

Further in a preferred approach for this aspect of the invention, theNDR FET is a pull-up element in the memory cell, and the bias signal isalso applied to a second NDR FET acting as a pull-down element of thememory cell.

In yet another aspect of the invention, an “erase before write”operation is performed for a memory cell, including an SRAM, byadjusting a bias signal to the pull-down and pull-up elements. This theneffectively erases the cell by placing the storage node in anindeterminate state. To do this, the bias signal is set to a firstamplitude, and then to a second amplitude that is less than the firstamplitude during the erase step. After the new data is written to thecell the bias signal is restored from the second amplitude back to thefirst amplitude. To control the cell in this fashion a bias controlsignal is generated, in response to initiation of a write operation, tocontrol signal characteristics of the bias signal, including anamplitude of such signal.

Other aspects of the invention concern operations which enhancecharacteristics of active elements for a memory cell, includingcharacteristics of read operations performed for an NDR based memorycell.

In a first aspect, an NDR based memory cell operates by applying a biassignal to the NDR-capable element, during a first operation period inwhich the memory cell is storing a data value, to enable the NDR-capableelement to operate with an NDR characteristic. The NDR characteristic isadjusted to facilitate storing of the data value in the memory cellduring a first storage operation. During a second operation period thebias signal is adjusted so as to enhance the NDR characteristic and acurrent drive characteristic of the NDR-capable element immediatelyprior to and/or during a second operation associated with the memorycell.

In this fashion, additional current can be provided to improve a readspeed for the memory cell. In a preferred approach, the NDR-capableelement includes an NDR field effect transistor (NDR FET). During theread operation, the bias signal is adjusted to have an amplitude that islarger than that used during quiescent storage mode. This allows an NDRmemory cell to be viable in a multi-megabit memory array, since a ratioof a quiescent current produced by the memory cell to a read operationcurrent (PVR) produced by the memory cell can exceed 10,000. Othertechniques for accelerating a read speed, such as precharging a BIT linecoupled to the memory cell, can also be employed.

Another aspect of the invention concerns adjusting the NDR behavior of amemory cell during a read operation, analogous to that explained abovefor a write operation—except that for a read operation the NDR behavioris enhanced rather than impaired.

These and other aspects of the invention are now described in detailwith reference to the figures provided herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a static random access memory (SRAM) cellconsisting of the combination of two NDR-FET elements which form abistable latch and one n-channel enhancement-mode IGFET access element;

FIG. 2 is a plot of the current-vs.-voltage characteristic of thebistable latch formed by the combination of two NDR-FETs as shown inFIG. 1;

FIG. 3A is a timing diagram illustrating the general sequence andrelationship of signals used in memory embodiments that incorporate apreferred writing method of the present invention;

FIG. 3B is a timing diagram illustrating the general sequence andrelationship of signals used in memory embodiments that incorporate apreferred reading method of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Various embodiments of the invention are now described.

As noted earlier, FIG. 1 is a circuit diagram of a preferred embodimentof a static memory (SRAM) cell 100 consisting of two NDR elements 120,130 that form a bistable latch 140 and one enhancement-mode IGFET accesselement 110. While a three (3) element implementation is shown in FIG.1, the invention is by no means limited to such embodiments, as otherdesigns employing NDR elements can also benefit from the presentteachings. Within cell 100 NDR element 120 can be considered a pull-downelement, or a driver element, while NDR element 130 is considered as apull-up element, or a load element as those terms are understood in thisfield of art.

FIG. 2 is a current-vs.-voltage plot illustrating the generaloperational characteristics of the static memory cell 100 of FIG. 1,including in a storage mode of operation. Again, it will be understoodby those skilled in the art that this Figure is merely intended to givean overall understanding of the general I-V characteristics of an NDRelement, and that the performance of any particular implementation ofthe invention may vary from that shown in FIG. 2 without straying fromthe scope of the present invention.

NDR elements 120, 130 of the present invention are preferably an NDR FETof the type referred to above in the aforementioned King et al.applications. The details of the same are provided for example in theaforementioned applications, and such documents are incorporated byreference herein primarily for the purpose of providing non-essentialbackground information on representative types of environments in whichthe present inventions can be practiced. Other types of silicon basedNDR FETs are clearly suitable and encompassed within the presentteachings, particularly to the extent their PVR performance can beenhanced through intelligent biasing as noted below.

Enhanced Write Operation

A preferred method for writing to an NDR based SRAM cell is nowdescribed. It will be understood by those skilled in the art that thepresent invention could be used with other memory devices (aside fromSRAMs of the type shown in the aforementioned Ser. No. 10/029,077),including for example those that utilize active elements having NDRcharacteristics.

In brief, to improve write access time, the NDR element (a metal oxidesemiconductor transistor—referred to as MOST herein, which is a type offield effect transistor (FET)) gate bias voltage(s) are pulsed low tolower the peak current of both NDR MOST transistors just prior toprogramming (word line pulsed high). The gate bias voltage(s) wouldreturn to the “normal” high-voltage state just after the word linevoltage reaches the high voltage state.

Viewed from an operational perspective, memory device 100 may beeffectively considered erased and set to a third logical state that isintermediate or between two extreme possible states (i.e., a highvoltage potential or a low voltage potential present on the storagenode). This state can also be characterized as indeterminate (in thesense that the ultimate ending state is uncertain or unpredictabledepending on the amount of time reserved for such operation), but whichis nonetheless “easier” (and faster) to write to, instead of having itstart off as a logical 0 state or logical 1 state. In a preferredapproach, storage node V_(SN) is set to a voltage potential that isabout half-way between V_(DD) and Ground (or V_(SS)) as seen in FIG. 1.This again, can be thought of as a form of directly pre-charging thestorage node or the memory cell in anticipation of the data value to bewritten. This procedure, therefore, may have advantages in other SRAMmemory environments aside from NDR based cells, as a type of erasebefore (or as part of) a write operation.

This operation is described in detail with reference to FIG. 3A. Priorto time t₀ the memory cell is in a quiescent mode of operation, in whichit is operating to store a particular data value. At this time a writebias disable/control signal is generated, causing both Vbias1 and Vbias2inputs to go from a normal NDR-capable voltage state to a lower voltagestate beginning at time t₁ and reaching a final low state at time t₂. Atthis point and in this form, the bias signals are adjusted to enhance awrite operation for the cell, and can be considered as write-enhancementsignals. Because NDR FETS 120 and 130 (FIG. 1) use a somewhat higherbias signal, it is possible to reduce Vbias1 and Vbias2 only by anamount needed (i.e, only partway to Vss) to lower the peak current ofthe NDR FETs (and thus disable the NDR behavior of such FETs as well).Accordingly, this operation can be accomplished in a very short periodof time. In a preferred embodiment NDR FETs 120 and 130 are connected toa common bias signal (i.e., Vbias1 and Vbias2 are the same).

At time t₃, a write signal is applied to transfer FET 110, and a newdata value is written (programmed) into memory cell 100 through the BITline in any conventional fashion during a write mode or write operationfor the cell. Since both NDR FETs are essentially disabled, they do notmaterially affect the write speed of a particular data value (0 or 1)into node V_(SN) during a write time t_(w) (which lasts until t₇). Attime t₄, the write bias control signal goes low, and thus at time t₅ therespective bias signals to the two NDR FETs begin to be restored totheir original state, so that at time t₆ the two NDR FETs againcontribute to the maintenance (latching) of the data value as writteninto the memory device (i.e., during a later storage mode) through theirrespective NDR characteristics.

It will be understood by those skilled in the art that the timing asshown in FIG. 3A is merely exemplary, and that other variations could bebeneficially employed and still be encompassed by the present invention.For example, when two input bias signals are used, they might beseparately disabled at different times; similarly, they may bere-enabled at different times. Furthermore, there may be some overlappermitted in some cases between when the write signal is activated (t₃)and the period in which the NDR bias signals are reaching their lowervoltage state (from t₁ to t₂). While the write Bias control is shown asa single signal, it will be understood that in fact its function can beachieved by several independent signals in accordance with standarddesign techniques.

Moreover, the diagram is not intended to be to scale, so the initiation,slew rate, amplitude and duration of the signals shown can be variedwithout departing from the spirit of the present invention. The variouscircuits required to implement the timing of FIG. 3A, including thegeneration of the write bias control (disable) signal based oninitiation of a write operation, and the adjustment of Vbias1 and Vbias2during a write operation or write mode, can be constructed by a varietyof means through ordinary design skill. The particulars of such circuitare not material to the present teachings, so the invention is by nomeans limited to any particular implementation of the same. In additionto controlling the signal amplitude level, other methods for controllingthe respective bias signals to the NDR FETs will be apparent to skilledartisans to achieve substantially the same result.

Thus, from this description it can be seen that both NDR FETs originallyin a storage operating mode are essentially weakened (or completelydisabled) just prior to the programming operation (or write mode) toreduce/eliminate any contribution to the write operation. The NDR FETsare turned on again before the write operation is finished so that theythen “latch” the stored data at node SN by their NDR behavior as notedin the aforementioned applications Ser. No. 10/029,077. This process hasthe additional benefit that overall power consumption is also reducedfor write operations as compared to prior techniques.

Looked at from another perspective, the present invention can be thoughtof as temporarily disabling an otherwise advantageous NDR behaviorduring certain operational time periods for a memory cell, such asduring selected portions of a write process. It is conceivable that itmay be also desirable to disable such NDR behavior during other times(power up, reset, test) for the memory cell, or in other circuits duringtheir normal operations; such are clearly contemplated by the presentteachings. Finally, other general memory cells/devices (not includingNDR elements) may benefit from selective enabling/disabling of pull-upand pull-down elements contained therein to enhance a write operation.

It will be understood, of course, that, at least for a write process, itmay not be necessary to completely disable such devices prior to suchoperation, and the overall write process may be improved significantlyeven by biasing techniques that merely impair or reduce theparticipation of the NDR FETs during selected portions (or all) of awrite operation.

This write enhancement of the present invention is extremely usefulbecause typically with reference to FIG. 1, if storage node VSN is at alow value, and a write operation is to be performed for a high value,then cell 100 does not get set to a stable operating point until an NDRbehavior of NDR element 120 shuts it off. At such time, node VSN is thuscompletely controlled by pull-up element 130 which sets it to a highpotential (i.e., VDD or thereabouts). A similar situation arises for theopposite case where a write operation is to be performed for a low valuewhen the storage node VSN is at a high value. Accordingly, a write-speedfor a typical NDR SRAM cell 100 is controlled by NDR switchingcharacteristics of NDR FETs 120 and 130. By disabling an NDRcharacteristic of the NDR FETs in advance of a write operation, theswitching time to stabilize a new value written to cell 100 is reducedbecause the NDR elements are at least partly shut off while the data isbeing written.

It should be noted that in some instances this type of write“enhancement” will not be necessary or desirable. For example, in caseswhere the overall write time (as shown in FIG. 3A) exceeds a periodrequired for a conventional write operation, it is preferable not to usethe aforementioned technique. This may be possible when the operatingcharacteristics of the NDR elements (their settling times) aresufficiently fast to pull the storage node up or down in a time quickerthan that possible using the enhanced technique noted above. Thislimiting factor, in turn will determine the extent to which the NDR FETelement bias voltages needs to be attenuated for any particularapplication.

Read Operation Enhancement

In a similar fashion, a further related aspect of the invention pertainsto a preferred method for reading an NDR based SRAM cell, such as thetype discussed above. Again, it will be understood by those skilled inthe art that the present invention could be used with other memorydevices (aside from SRAM), including those that utilize active elementshaving NDR characteristics.

In summary, to improve read access time during a read mode, the NDR FETgate bias voltage(s) are pulsed to a higher-than-“normal” voltage justbefore the word line is pulsed high. The resulting higher peak currentcharges the bit line faster, for faster read access time. After the readoperation is completed, the gate bias voltages are then returned to the“normal” high-voltage state just after the word line returns to thelow-voltage state to ensure proper maintenance of the data value duringa subsequent storage mode.

Viewed from another perspective, it can be seen that in contrast to thewrite enhancement operation described earlier, the NDR FETs in the readenhancement method of the present invention have their peak current (andto some extent their NDR behavior) effectively “enhanced” rather thenreduced (or disabled) during a read mode. In this manner, the overallpeak-to-valley ratio (PVR) of a memory cell using NDR devices can beenhanced by such technique. In other words, the peak current of thememory cell is increased without a corresponding increase in the valleycurrent, because the “boost” to the current is performed only duringportions (or all of) a read operation. Furthermore, the NDR FETs of thepresent invention are characterized by the fact that a peak currentincreases with increasing applied gate voltage (i.e., in a non-NDRoperating region) but the valley current does not increase as quicklywith increasing applied gate voltage. Thus, the PVR improves generallyas a function of a gate drive applied to NDR FETs 120 and 130, and thisaspect can be exploited in SRAM embodiments through dynamically varyingthe gate bias signals as explained herein. By this same principle,therefore, the PVR for any particular embodiment, such as for a lowpower embodiment, can also be improved by reducing gate bias signals toNDR FETs 120, 130 to reduce a valley current, just as they were raisedduring a sense or read mode to increase a peak current. Furthermore,unlike many other prior art devices, by using NDR FETs in an SRAM cell,the PVR is substantially more constant over temperature, and this is yetanother benefit of using such technology.

The preferred reading method is described in detail with reference toFIG. 3B. Prior to a read mode, the memory cell is in a quiescent storagemode as noted earlier. Just before a read operation commences, namely,at time to, a read bias control (in this case, a read enhancement)signal is generated, causing both Vbias1 and Vbias2 inputs to go from anormal NDR-capable voltage state to a higher voltage state starting attime t₁ and reaching a final high state at time t₂. At this point and inthis form, the bias signals are adjusted to be enhance a read operationfor the cell, and can be considered as read-enhancement signals. Again,in a preferred embodiment, as noted earlier, both NDR FETs are connectedto a common bias line and bias signal.

Because NDR FETS provide a drive current proportional to their gatevoltage, it is possible to boost Vbias1 and Vbias2 by a controlledamount which also increases the NDR behavior of such FETs. Accordingly,this read operation can be accomplished in a very short period of time.At time t₃, a read signal is applied to transfer FET 140, and a datavalue stored in memory cell 100 is read through the bit line.

Note that to improve operational speed for higher speed applications,the bit line can be precharged to a value midway a logical 0 and logical1 state (typically, Vdd/2) so that it is either pulled high or low morequickly than if it were starting from a fixed potential that is high orlow. In addition, a reference cell (not shown) can be used to allowdifferential sensing against a sensed cell in a manner akin to that ofconventional memory cells and differential sense amplifiers. Othertechniques for increasing read time performance will be apparent tothose skilled in the art.

Since both NDR FETs are essentially enhanced during parts or all of aread mode or read operation, they help to provide an additional drivecurrent during the reading of a particular data value (0 or 1) in nodeV_(SN) during a read time t_(R) (which lasts until t₄). At time t₅, theread bias control (NDR enhancement) signal goes low again, so that thetwo NDR FET bias signals are returned to their normal operating valuebeginning at time t₆ and finishing at time t₇. Thereafter they againcontribute to the maintenance (latching) of the data value as storedinto the memory device through their NDR characteristics.

Because there is no adverse effect from enhancing the NDR behaviorduring the read process, it is not necessary to return the NDR FETs totheir normal operating bias prior to completion of the read operation.Nonetheless, this could be done if desired by appropriate adjustment ofthe bias control signal.

One consequence of using two NDR FETs is that the overall read (orsensing) speed of cell 100 is not limited or tied to an NDR switchingspeed of an NDR element (i.e., between an NDR region and a non-NDRregion). This is advantageous for scaling purposes as well.

As with FIG. 3A, it will be understood by those skilled in the art thatthe timing as shown in FIG. 3B is merely exemplary, and that othervariations could be beneficially employed with the present invention.For example, the two input bias signals Vbias1 and Vbias2 might beseparately enhanced at different times; similarly, they may be returnedto normal values at different times, and even, as alluded to before,during the time the read signal is still high. Furthermore, there may besome overlap permitted in some cases between when the read signal isactivated (t₃) and the period in which the NDR bias signals are reachingtheir higher voltage state (from t₁ to t₂), or conversely when the readsignal is deactivated (t₄) and the period in which the NDR bias signalsare returning to their normal voltage state (from t₆ to t₇). Finally, asnoted earlier, while the read Bias control signal is shown as a singlesignal, it will be understood that in fact its function can be achievedby several independent signals in accordance with standard designtechniques.

Moreover, the diagram of FIG. 3B is not intended to be to scale, so theinitiation, slew rate, amplitude and duration of the signals shown canbe varied without departing from the spirit of the present invention.The various circuits required to implement the timing of FIG. 3B,including the generation of the bias enhancement signal in response toan initiation of a read operation, and the boosting of Vbias1 and Vbias2can be constructed by a variety of means through ordinary design skill.The particulars of such circuit are not material to the presentteachings, so the invention is by no means limited to any particularimplementation of the same.

Looked at from another perspective, this facet of the present inventioncan be thought of as temporarily enhancing an NDR behavior duringcertain operational time periods for a memory cell, such as during aread process. It is conceivable that it may be also desirable to boostsuch NDR behavior during other times (power up, reset, test) for thememory cell, or in other circuits during their normal operations; suchare clearly contemplated by the present teachings. Finally, as notedearlier for the write enhancement method of the present invention, othergeneral memory cells/devices (not including NDR elements) may benefitfrom selective enabling/disabling of pull-up and pull-down elementscontained therein during read operations.

Thus, both a write operation and a read operation can be controlled andenhanced by suitable scaling/adjustment of the bias signals provided tothe NDR FETs of an NDR SRAM cells. The bias signals thus operatedeffectuate a type of a read control signal and write control signal forsuch types of memory devices.

Finally it is apparent, of course, that memory devices operating inaccordance herein may utilize one or both of the read/write enhancementsdisclosed depending on the intended application, manufacturinglimitations and required performance characteristics.

While the invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. It will be clearly understood by those skilled in theart that foregoing description is merely by way of example and is not alimitation on the scope of the invention, which may be utilized in manytypes of integrated circuits made with conventional processingtechnologies. Various modifications and combinations of the illustrativeembodiments, as well as other embodiments of the invention, will beapparent to persons skilled in the art upon reference to thedescription. Such modifications and combinations, of course, may useother features that are already known in lieu of or in addition to whatis disclosed herein. It is therefore intended that the appended claimsencompass any such modifications or embodiments. While such claims havebeen formulated based on the particular embodiments described herein, itshould be apparent the scope of the disclosure herein also applies toany novel and non-obvious feature (or combination thereof) disclosedexplicitly or implicitly to one of skill in the art, regardless ofwhether such relates to the claims as provided below, and whether or notit solves and/or mitigates all of the same technical problems describedabove. Finally, the applicants further reserve the right to pursue newand/or additional claims directed to any such novel and non-obviousfeatures during the prosecution of the present application (and/or anyrelated applications).

1. A method of operating a memory cell that includes a negative differential resistance (NDR) capable element, comprising the steps of: (a) applying a bias signal to the NDR-capable element, during a first operation period in which the memory cell is storing a data value, to enable the NDR-capable element to operate with an NDR characteristic; wherein said NDR characteristic is adjusted to facilitate storing of said data value in the memory cell during a first storage operation; (b) adjusting said bias signal, during a second operation period, so as to disable said NDR characteristic immediately prior to and/or during a second operation associated with the memory cell.
 2. The method of claim 1, wherein said second operation is a write operation.
 3. The method of claim, wherein the NDR-capable element is an NDR field effect transistor (FET) and said NDR characteristic is exhibited in a channel region of said NDR FET.
 4. The method of claim 3, wherein said bias signal is adjusted so that is reduced below a threshold voltage required to activate said NDR characteristic in said NDR FET.
 5. The method of claim 1, further including a step: adjusting said bias signal during said second operation period to re-enable said NDR characteristic and facilitate storing of a new data value written to the memory cell during said second operation.
 6. A method of operating a memory cell that includes a negative differential resistance (NDR) element, comprising the steps of: (a) applying a bias signal to the NDR element during a first period in which the memory cell is storing a data value, said bias signal having a first signal characteristic during said first period so as to control the NDR element to have a first NDR characteristic; and (b) adjusting said bias signal to have a second signal characteristic during a second period, so as to control the NDR element to have a second NDR characteristic immediately prior to and/or during a write operation associated with the memory cell.
 7. The method of claim 6, wherein said first signal characteristic is a first signal voltage amplitude level associated with said bias signal, and said second signal characteristic is a second signal voltage amplitude level associated with said bias signal.
 8. The method of claim 7, wherein said first signal voltage amplitude level is greater than said second signal voltage amplitude level so that the first NDR characteristic includes an NDR operating region and the second NDR characteristic does not include an NDR operating region.
 9. The method of claim 7, wherein said first signal voltage amplitude level is greater than said second signal voltage amplitude level so that the first NDR characteristic includes a relatively high peak current and the second NDR characteristic includes a relatively lower peak current.
 10. The method of claim 6, wherein said data value is erased before said write operation effectuates writing of a subsequent data value to the memory cell.
 11. The method of claim 6, wherein the NDR element is a first NDR element, and said bias signal is applied to a second NDR element of the memory cell as well at substantially the same time during said first period and said second period.
 12. A method of operating a memory cell that includes a negative differential resistance (NDR) field effect transistor (FET) comprising the steps of: (a) applying a bias signal to the NDR FET to cause it to operate with an NDR characteristic; and (b) erasing a first data value stored in the memory cell, immediately prior to a write operation, by adjusting said bias signal to attenuate and/or disable said NDR characteristic, said first data value comprising at least a first voltage potential or a second voltage potential present in a storage node of the memory cell; wherein said erasing step also sets said storage node to a third voltage potential, said third voltage potential being set without regard to a voltage potential associated with a second data value to be written to the memory cell; (c) writing said second data value to the memory cell during a write operation under control of a write signal to adjust the storage node from said third voltage potential to one of at least said first voltage potential or said second voltage potential.
 13. The method of claim 12, wherein said third voltage potential corresponds to a voltage potential that is approximately half-way between said first voltage potential and said second voltage potential.
 14. The method of claim 12, wherein said third voltage potential corresponds to either said first voltage potential or said second voltage potential.
 15. The method of claim 12, wherein the NDR FET is a pull-up element in the memory cell, and said bias signal is also applied to a second NDR FET acting as a pull-down element of the memory cell.
 16. A method of operating a memory cell comprising the steps of: (a) applying a bias signal to a pull-up element to cause it to store a first data value at a storage node, said first data value comprising at least a first logic level or a second logic level; (b) erasing said first data value stored in the memory cell, immediately prior to a write operation, by controlling said bias signal; wherein said erasing step also sets the memory cell to a third logic level, said third logic level being an indeterminate level between said first logic level and said second logic level; (c) writing a second data value to the memory cell during a write operation under control of a write signal to set the memory cell to said first logic level or said second logic level.
 17. The method of claim 16, further including a step: applying said bias signal to a pull-down element of the memory cell at least during steps (a) and (b).
 18. The method of claim 16, wherein during step (a) said bias signal is set to a first amplitude, during step (b) said bias signal is set to a second amplitude that is less than said first amplitude, and during step (c) said bias signal is adjusted from said second amplitude back to said first amplitude.
 19. The method of claim 16, further including a step: generating a bias control signal, in response to initiation of a write operation, to control signal characteristics of said bias signal, including an amplitude of such signal.
 20. The method of claim 16, wherein the memory cell includes one or more negative differential resistance (NDR) elements receiving said bias signal, including at least one NDR field effect transistor.
 21. A method of operating a memory cell that includes a negative differential resistance (NDR) capable element, comprising the steps of: (a) applying a bias signal to the NDR-capable element, during a first operation period in which the memory cell is storing a data value, to enable the NDR-capable element to operate with an NDR characteristic; wherein said NDR characteristic is adjusted to facilitate storing of said data value in the memory cell during a first storage operation; (b) adjusting said bias signal, during a second operation period, so as to enhance said NDR characteristic and a current drive characteristic of the NDR-capable element immediately prior to and/or during a second operation associated with the memory cell.
 22. The method of claim 21, wherein the NDR-capable element includes an NDR field effect transistor (NDR FET).
 23. The method of claim 21, wherein said second operation is a read operation.
 24. The method of claim 21, wherein during step (b) said bias signal is adjusted to have an amplitude that is larger than during step (a).
 25. The method of claim 24, wherein after step (b) is completed, said bias signal is again adjusted to have an amplitude equal to that used in step (a).
 26. The method of claim 21, wherein a ratio of a quiescent current produced by the memory cell to a read operation current produced by the memory cell exceeds 10,000 to enable the memory cell to operate as part of a multi-megabit memory array.
 27. The method of claim 23, further including a step: precharging a BIT line coupled to the memory cell to accelerate said read operation.
 28. A method of operating a memory cell that includes a negative differential resistance (NDR) capable element, comprising the steps of: (a) applying a bias signal to the NDR-capable element, during a first operation period in which the memory cell is storing a data value, to enable the NDR-capable element to operate with a first peak current characteristic; wherein said first peak current characteristic is adjusted to facilitate storing of said data value in the memory cell during a first storage operation; (b) adjusting said bias signal, during a second operation period, so as to lower said first peak current characteristic immediately prior to and/or during a second operation associated with the memory cell.
 29. The method of claim 28, wherein said second operation is a write operation.
 30. The method of claim 28, wherein the NDR-capable element is an NDR field effect transistor (FET).
 31. The method of claim 30, wherein said bias signal is adjusted so that is reduced below a threshold voltage required to activate an NDR characteristic in said NDR FET.
 32. The method of claim 28, further including a step: adjusting said bias signal during said second operation period to re-enable said first peak current characteristic and facilitate storing of a new data value written to the memory cell during said second operation.
 33. A method of operating a memory cell that includes a negative differential resistance (NDR) element, comprising the steps of: applying a bias signal to the NDR element during a first period in which the memory cell is storing a data value, said bias signal having a first signal characteristic during said first period so as to control the NDR element to have a first NDR characteristic; adjusting said bias signal to have a second characteristic during a second period, so as to control the NDR element to have a second NDR characteristic immediately prior to and/or during a read operation associated with the memory cell.
 34. A method of operating a memory cell comprising the steps of: applying a bias signal to at least one of a pull-up element or a pull-down element coupling a storage node to a first potential, during a first operation period in which the memory cell is storing a data value, to maintain said data value at said storage node in accordance with said first potential; adjusting said bias signal, during a second operation period, so as to enhance a current drive characteristic of the pull-up element and/or pull-down element imediately prior to and/or during a read operation associated with the memory cell.
 35. In a memory device having three active elements, including a transfer field effect transistor (FET), a first negative differential resistance (NDR) element and a second NDR element that are operably interconnected to store a data value, the improvement comprising the steps of: applying a variable bias signal directly to at least one of the first NDR element and the second NDR element to control a current path that exhibits NDR behavior during operation of the memory device; wherein said variable bias signal is configured at a first value during a period when the memory device is storing the data value, and said variable bias signal is configured at a second value at least during a period when the data value is being written to or read from the memory device.
 36. In a memory device having including a transfer field effect transistor (FET), a first pull-down element and a pull-up element that are operably interconnected to store a data value at a storage node, the data value being represented by at least a first voltage state or a second voltage state, the improvement comprising the steps of: applying a variable bias signal directly to at least one of the first pull-down clement and the pull-up element to control current characteristics of a current path coupling the storage node to a first voltage potential; wherein said variable bias signal is set to a first value during a period when the memory device is storing the data value, and said variable bias signal is set to a second value immediately prior at least during a period when the data value is being written to the memory device so as to disable said current path and place such storage node in an intermediate voltage potential state.
 37. In a memory device having including a transfer field effect transistor (FET), a first pull-down element and a pull-up element that arc operably interconnected to store a data value at a storage node, the improvement comprising the steps of: applying a variable bias signal directly to at least one of the first pull-down element and the pull-up element to control current characteristics of a current path coupling the storage node to a first voltage potential; wherein said variable bias signal is set to a first value during a period when the memory device is storing the data value, and said variable bias signal is set to a second value immediately prior at least during a period when the data value is being read from the memory device so as to increase an amount of current that can be carried in said current path and increase a read speed for the memory device.
 38. In a memory cell consisting of at most three active elements, including a transfer field effect transistor (FET), a first negative differential resistance (NDR) FET and a second NDR FET that are operably interconnected to store a first data value, the first data value being represented by at least a first voltage state or a second voltage state, the improvement comprising the steps of: (a) applying a first bias signal to the first NDR FET during a storage operation of the memory cell so as to control storing the first data value using a first NDR characteristic of said first NDR FET; and (b) applying a second bias signal to the second NDR FET and the second NDR FET during a storage operation of the memory cell so as to control storing the first data value using NDR characteristics of said first NDR FET and said second NDR FET; and (c) modifying said first bias signal and said second bias signal during a write operation to the memory cell to generate a write-enhancement first bias signal and a write-enhancement second bias signal; and wherein said write-enhancement first bias signal and said write-enhancement second bias signal are adapted to erase the data value and set the memory cell to a third voltage state immediately prior to writing a subsequent data value to the memory cell, said third voltage state being intermediate said first voltage state and said second voltage state; (d) modifying said first bias signal and said second bias signal during a read operation to the memory cell to generate a read-enhancement first bias signal and a read-enhancement second bias signal; and wherein said read-enhancement first bias signal and said read-enhancement second bias signal are adapted to enhance current drive characteristics of the first NDR FET and the second NDR FET during said read operation. 